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ASIC and FPGA Workflow for ISO 26262 and IEC 61508

Get an overview of HDL code generation and verification support in IEC Certification Kit for ISO 26262 and IEC 61508.

IEC Certification Kit for ISO 26262 and IEC 61508 has added workflow and artifact documentation for connecting Model-Based Design for functional safety to ASIC and FPGA implementation. This includes the certificate from TÜV SÜD showing that HDL Coder is qualified according to ISO 26262 for any ASIL, and has also been tested for suitability according to IEC 61508, IEC 62304, EN 50128, and ISO 25119.

This workflow includes:

- Requirements authoring
- Architectural modeling
- Implementation modeling
- Static model analysis in Model Advisor
- HDL code generation
- Validation and verification at every step, including generation of models for downstream RTL verification

The kit also provides templates for managing and documenting your workflow steps and artifacts. And if you require more extensive support in deploying this process, MathWorks offers an ISO 26262 Process Deployment Advisory Service - To learn more about the MathWorks ISO 26262 workflow, visit ISO 26262 support in MATLAB and Simulink -

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