How to Automatically Detect Design Errors in Your Simulink Models

You can use Simulink Design Verifier™ to automatically detect design errors early in the development process. This saves a lot of development and test time. Supported design errors include dead logic, division-by-zero, and many others.

In this video, you’ll see how to use Simulink Design Verifier in order to find errors in a design, and how errors, when detected, can be debugged using the visualization features in Simulink Design Verifier.

You’ll also see how Simulink Design Verifier provides a test case for run-time errors, which can be debugged using the debugging capabilities in Simulink, simplifying the process of understanding the cause of an error.

Additional Information: - Simulink Design Verifier: https://bit.ly/36r06aB - Example of design error detection (for integer overflow): https://bit.ly/2E6p2bd