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FPGA Design with MATLAB, Part 1: Why Use MATLAB and Simulink

HDL Coder™ generates synthesizable VHDL® or Verilog® RTL from MATLAB® functions, Simulink® models, and Stateflow® charts that can be used to target FPGA or ASIC hardware. This tutorial uses a simple signal-processing algorithm to show the typical steps our customers follow to adapt their high-level algorithms with hardware architecture detail so they can be implemented efficiently in hardware and verified at each step.

This video covers:

- Key considerations for hardware design: streaming data and fixed resources
- Strengths of MATLAB and Simulink and how to leverage each for hardware design
- Overview of the workflow, including verification of each step
- HDL Coder Self-Guided Tutorial overview
- Introduction to the MATLAB golden reference algorithm
- Adapting the frame-based algorithm to a streaming algorithm

Get HDL Coder Self-Guided Tutorial:

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