FPGA Design with MATLAB, Part 3: Architecting Efficient Hardware

Generating an efficient FPGA design generally involves balancing the throughput, latency, and hardware resources. Depending on the nature of your design and your goals, there are a number of ways to adapt your algorithm for efficient hardware implementation. This part of the tutorial showcases a few of the methods.

This video covers:

- Setting the model parameters for HDL code generation
- How the Simulink® model's sample rate translates to the clock rate of the FPGA hardware
- Inserting pipeline registers using various optimization techniques on the data paths
- Use of data valid control signal to monitor the input sample data
- Verification of the optimized architecture using a MATLAB® test bench

Get HDL Coder Self-Guided Tutorial: https://bit.ly/2X7Va5y

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