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Introduction to FPGA Verification with MATLAB and Simulink

A 2018 study revealed that 84% of FPGA design projects – including some safety-critical designs - suffered from non-trivial bugs escaping into production, with 10% having four or more bugs released into production.

In this webinar, MathWorks engineers will demonstrate a series of techniques that FPGA design teams in industry are using today to verify correct performance of FPGA designs using MATLAB and Simulink.

    Use MATLAB and Simulink test benches to verify that RTL implementations conform to specification models, then use these same test benches to verify implementation on with hardware testing on FPGA and SoC boards.
    Debug FPGA implementations from MATLAB and Simulink by inserting probes and triggers within designs to capture internal signals during hardware testing and analyzing results in MATLAB.
    Use test harnesses in Simulink to achieve Simulink test benches with high levels of functional coverage, then generate SystemVerilog or UVM test bench components automatically for use in production verification environments.

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