Adopting Model-Based Design for FPGA, ASIC, and SoC Development

Connecting MATLAB® and Simulink® to digital hardware design and verification has helped numerous customers (examples below) shorten their schedules, improve their verification productivity, and deliver higher quality of results in their FPGA, ASIC, or SoC design processes. While this workflow may seem very different from your existing workflow, you can adopt it incrementally while realizing immediate benefits.

Learn how to:

- Use the strengths of both MATLAB and Simulink together to collaborate to refine your algorithms with more implementation detail
- Build a reusable test bench infrastructure
- Generate SystemVerilog verification components to speed development of your RTL verification environment
- Collaborate between algorithm and digital hardware engineers to converge early on efficient hardware architectures
- Automate and manage the fixed-point conversion process, and even take advantage of native floating-point implementation where it’s more efficient
- Generate error-free synthesizable RTL to target any FPGA, ASIC, or SoC device

This overview outlines proven methods for getting started, along with typical adoption paths from there.

Examples:

A Mixed-Signal Model-Based Design Flow for Automotive Sensors: https://bit.ly/31TAth0
Ultra-Low Power Model-Based ASIC Design for Implantable Medical Products Using HDL Coder: https://bit.ly/2J970qK
Driving the Adoption of Model-Based Design for Communications System Development at Hitachi: https://bit.ly/2X9AzCE
5G R&D at Huawei: An Insider Look: https://bit.ly/2xbI2Sa

Other Resources
Learn about HDL Code Generation and Verification: https://bit.ly/2x9QP7h
Improve RTL Verification by Connecting to MATLAB: https://bit.ly/31XtzHw
FPGA for DSP Applications: Fixed Point Made Easy: https://bit.ly/2J2nsJy
HDL Coder Self-Guided Tutorial: https://bit.ly/2X7Va5y

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